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Flip-Flops and Sequential Logic

Logic that remembers — how a bit is stored, the latch and the edge-triggered flip-flop, the D/JK/T types, and the registers, counters, and shift registers built from them.

IntermediateLow Risk27 min read

What You Will Learn

  • You will learn the difference between combinational logic (no memory) and sequential logic (memory), and how a flip-flop stores one bit.
  • You will learn how a simple SR latch is built from cross-coupled gates, and the difference between a level-sensitive latch and an edge-triggered flip-flop.
  • You will learn the common flip-flop types — SR, D, JK, and T — and what each one does.
  • You will learn the building blocks made from flip-flops — registers, counters, and shift registers — and how to reason about a stuck-bit or clock fault.

What You Will Be Able To Do

  • You will be able to distinguish combinational from sequential logic and explain how a flip-flop remembers a bit.
  • You will be able to describe an SR latch and the difference between a latch and an edge-triggered flip-flop.
  • You will be able to state what a D, JK, and T flip-flop each do, including the T's divide-by-2.
  • You will be able to identify a register, counter, and shift register and reason about a sequential-logic fault.

Required Tools

No physical tools required. This is a conceptual section.

Section Overview

The gates of Section 6.1 have no memory: their output depends only on what their inputs are right now. That's combinational logic. This section adds the missing ingredient — memory — to reach sequential logic, where the output depends on the inputs and on the stored past. The device that stores a bit is the flip-flop: a circuit that stably holds a 1 or a 0 until told to change. You'll see how memory emerges from ordinary gates (a latch made of cross-coupled gates that feed back to hold their state), the crucial difference between a level-sensitive latch and an edge-triggered flip-flop, the common flip-flop types (SR, D, JK, T), and the building blocks made from them — a register, a counter, and a shift register. This is the leap from logic that computes to logic that remembers, and it underlies every processor, memory, and state machine.

Why This Matters

Nothing digital would work without memory. A processor needs registers to hold values, a counter to track steps, a state machine to know where it is in a sequence — all built from flip-flops. Sequential logic is what turns static gates into systems that do things over time. For a repair technician, the shift to sequential logic adds new failure signatures to recognize: a bit stuck and refusing to change, a counter that won't count, a register that won't load, a flip-flop that isn't being clocked. And it introduces the clock as the heartbeat of digital systems — the shared timing signal (detailed in the next section) that steps everything forward together. Understanding how a flip-flop stores a bit and how the common types behave is the foundation for reading and diagnosing any clocked digital circuit.

Required Prerequisites

No consumables required. A couple of flip-flop ICs (a 7474 dual D flip-flop, a 7476 JK) make ideal, reusable study material, but nothing is used up.

  • Optional: a D or JK flip-flop IC (a 74xx or 40xx part), a breadboard, a low-voltage supply, a debounced switch or slow pulse source for a clock, and LEDs to watch the stored bit
  • A logic probe or multimeter to read the stored HIGH/LOW state
  • No special hardware is required; the section stands on the concepts

Real-World Applications

Flip-flops and sequential logic are everywhere a system must remember or count. Registers inside every processor hold the values being worked on; memory is built from vast arrays of storage cells; counters measure time, divide clock frequencies, and track events; shift registers convert data between serial and parallel form (the basis of much communication, coming in Section 6.4). A frequency divider in a clock circuit is a chain of T flip-flops. A state machine sequencing a washing machine, a traffic light, or a communication protocol is flip-flops plus logic. On a real board, the clocked ICs — registers, counters, latches — are sequential logic, and recognizing them, knowing what they should do on each clock, and spotting a bit that won't change is a core digital-diagnosis skill.

Common Challenges

  • Expecting an output to depend only on the inputs. In sequential logic the output also depends on the stored state, so the same inputs can give different outputs depending on what happened before. That's the whole point of memory, and it's the mental shift from combinational thinking.
  • Confusing a latch with a flip-flop. A latch follows its input while its enable is at a level; a flip-flop captures its input only at a clock edge. They behave very differently around timing, and mixing them up leads to wrong expectations.
  • Forgetting the clock. Sequential logic changes state on the clock. If the clock isn't running (or isn't reaching a flip-flop), the state simply won't update — a common cause of "stuck" behavior that looks like a dead chip.

Safety Notes

Risk Level: Low. Sequential logic is low-voltage, signal-level, and safe to study and probe. The same two practical notes from the gates section apply.

Professional Tips Before Starting

  • Ask "does this circuit remember?" If an output depends on history, not just present inputs, it's sequential and there's a flip-flop (or memory) involved — look for the clock and the stored state.
  • Distinguish level from edge. A latch acts while its enable is at a level; a flip-flop acts only at the clock edge. Knowing which you're looking at tells you when the stored bit can change.
  • Check the clock first on a "stuck" digital circuit. A flip-flop that never updates is very often not being clocked — a missing, stopped, or blocked clock — before it's a failed chip.

Understanding Flip-Flops and Sequential Logic

Combinational vs Sequential: Adding Memory

The gates from Section 6.1 are combinational: their output is a pure function of their inputs at this moment, with no memory of the past. Feed the same inputs and you always get the same output. Sequential logic adds memory: its output depends on the current inputs and on a stored internal state, so the same inputs can produce different outputs depending on what came before. That stored state is what lets digital systems count, remember, and step through sequences — everything that happens over time rather than instantly. The element that holds the state is the flip-flop.

How Memory Emerges: The SR Latch

Memory doesn't need anything exotic — it emerges from ordinary gates connected so their outputs feed back to their inputs. The simplest example is the SR latch (Set-Reset), built from two cross-coupled NAND or NOR gates (the gates from Section 6.1). Each gate's output drives the other's input, so once the pair settles into a state, that feedback holds it: the circuit remembers. It has two control inputs. Asserting Set forces the stored bit (the output, called Q) to 1; asserting Reset forces Q to 0; asserting neither leaves Q holding its last value — that "hold" is the memory. There is also one input combination to avoid: asserting Set and Reset at the same time is invalid, because it asks the latch to be both 1 and 0 at once and leaves the outputs in a contradictory, unpredictable state. The SR latch is the fundamental one-bit memory cell, and every flip-flop is a refinement of this feed-back-to-hold idea.

Latch vs Flip-Flop: Level versus Edge

There's a crucial distinction in when a storage element responds. A latch is level-sensitive: while its enable (or clock) input is at the active level, it follows its data input, and it only holds when the enable goes inactive. A flip-flop is edge-triggered: it captures its data input only at the instant the clock changes — the rising edge (LOW to HIGH) or falling edge (HIGH to LOW) — and holds that value until the next edge, ignoring the input the rest of the time. This edge-triggering is what makes synchronous digital systems predictable: every flip-flop in the system captures its input at the same clock edge, so the whole machine advances one well-defined step at a time. The clock (detailed in Section 6.3) is the shared signal whose edges drive them all.

The Flip-Flop Types: SR, D, JK, T

A few flip-flop types cover most of what you'll meet:

  • SR — the set/reset behavior of the latch, in edge-triggered form: set makes Q 1, reset makes Q 0, with the both-asserted case still to be avoided.
  • D (Data) — the workhorse. A D flip-flop simply captures whatever is on its D input at the clock edge and holds it on Q until the next edge. "Whatever D is at the edge, Q becomes." This is the building block of registers and memory, because it cleanly stores one bit per clock.
  • JK — the versatile one. With its two inputs (J and K) a JK flip-flop can set, reset, hold, or toggle (flip to the opposite state) depending on the input combination, and it has no invalid state. It's the Swiss-army flip-flop.
  • T (Toggle) — flips its stored state on every clock edge (it's a JK with both inputs tied active). Because it changes state once per clock edge, its output completes one full cycle every two input clocks — so a T flip-flop divides the clock frequency by 2. Chain them and each stage halves the frequency again, which is how binary counters and frequency dividers are built.

Building Blocks: Registers, Counters, Shift Registers

Combine flip-flops and you get the workhorses of digital systems:

  • Register — several flip-flops sharing a clock, storing a multi-bit word (say 8 bits) all captured together on the clock edge. Registers hold the values a processor works with.
  • Counter — flip-flops arranged to count clock pulses. Chaining T flip-flops (each dividing by 2) produces a binary counter whose bits step through the count; counters measure time, divide frequencies, and track events.
  • Shift register — a chain of flip-flops that passes a bit from one to the next on each clock, shifting the data along. Shift registers convert between serial and parallel data — one bit at a time in, a whole word out (or vice versa) — the basis of much of the communication in Section 6.4.

And more broadly, memory plus logic makes a state machine: a circuit that steps through a defined sequence of states, deciding its next state from its current state and inputs. State machines sequence everything from a protocol to an appliance's controller — the essence of sequential logic doing useful work.

Common Mistakes

  • Treating sequential logic like combinational. The output depends on stored state, not just present inputs; the same inputs can give different results.
  • Mixing up latch and flip-flop. Level-sensitive latch versus edge-triggered flip-flop — they respond at different times, and expecting one to behave like the other causes confusion.
  • Overlooking a missing clock. A flip-flop that won't change state is often simply not being clocked; check the clock before condemning the chip.
  • Using the SR latch's invalid state. Asserting Set and Reset together leaves an SR latch in an undefined state; it's a combination to avoid, not use.

Troubleshooting Guidance

Sequential-logic faults have their own signatures, and the clock is central to all of them. When a bit or output is stuck — never changing no matter the inputs — first ask whether the flip-flop is even being clocked: probe the clock line at the chip, because a missing, stopped, or blocked clock means the stored state can never update, and this masquerades as a dead chip more often than a real failure does (the check-the-clock habit is the sequential cousin of check-power-first). If the clock is present and toggling, then compare the flip-flop's behavior to its type: a D flip-flop should show Q take the value of D at each clock edge; a T or counter stage should toggle or advance each clock; a register should load its inputs on the clock. An output that doesn't follow its type's rule points at the flip-flop, its inputs, or its reset/enable lines (a flip-flop held in reset, or with its enable deasserted, also won't update — check those control lines). Watch for a counter that skips or won't count (a clock, reset, or a failed stage) and a register that won't load (a clock or enable problem). And know one honest subtlety: metastability. If an edge-triggered input changes too close to the clock edge — violating the flip-flop's setup/hold timing — the output can momentarily hover in an undefined, in-between state before settling, causing rare, hard-to-reproduce glitches; it's why asynchronous signals are synchronized carefully. Deeper timing analysis comes in Section 6.3, but the diagnostic core is here: confirm the clock, then check each flip-flop against what its type should do.

Verification & Testing Methods

Check your understanding before moving on:

  • [ ] Explain the difference between combinational and sequential logic and how a flip-flop stores a bit.
  • [ ] Describe how an SR latch holds its state and the difference between a level-sensitive latch and an edge-triggered flip-flop.
  • [ ] State what a D, a JK, and a T flip-flop each do, including the T flip-flop's divide-by-2.
  • [ ] Identify a register, a counter, and a shift register, and explain why checking the clock comes first on a stuck sequential circuit.

Then try the practice exercises below — reasoning about memory and flip-flop behavior, no powered work required.

Practice Exercises

  1. Combinational or sequential? (5 minutes, reasoning). For each, say whether it is combinational or sequential and why: (a) an AND gate; (b) a circuit whose output counts how many button presses have occurred; (c) an XOR gate; (d) an 8-bit register holding a value.
  2. Name the flip-flop (5 minutes, reasoning). Which flip-flop type fits each need: (a) capture and hold one data bit each clock; (b) flip state every clock to divide a frequency by 2; (c) a versatile cell that can set, reset, hold, or toggle with no invalid state?
  3. The SR latch (10 minutes, reasoning). Describe how two cross-coupled gates hold a bit, what Set and Reset each do to Q, and why asserting both at once is a combination to avoid.
  4. Diagnose a stuck bit (10 minutes, reasoning). A register's output never changes when it should be loading new values. List, in order, what you'd check — starting with the reason a stuck sequential circuit most often has — and explain how a missing clock would produce exactly this symptom.

These core ideas — combinational vs sequential, the SR latch and latch-vs-flip-flop distinction, the D/JK/T types, and the registers/counters/shift registers built from them — are tested in the Chapter Quiz at the end of this chapter, where a score of 80% is required to continue.

Key Takeaways

  • Combinational logic has no memory (output depends only on present inputs); sequential logic adds memory, so the output depends on the inputs and a stored state — the basis of counting, remembering, and stepping through sequences.
  • A flip-flop stably stores one bit until told to change; memory emerges from gates via feedback, as in the latch (cross-coupled gates that hold their state).
  • The SR latch is the fundamental cell: Set forces Q to 1, Reset forces Q to 0, neither holds the last value, and asserting both is invalid.
  • A latch is level-sensitive (follows its input while enabled) while a flip-flop is edge-triggered (captures its input only at the clock edge) — edge-triggering is what makes synchronous systems advance one predictable step per clock.
  • The types: D captures its data input at the edge (the register/memory workhorse); JK can set, reset, hold, or toggle with no invalid state; T toggles each edge, dividing the clock frequency by 2.
  • Flip-flops build the register (multi-bit store), the counter (counts clock pulses), and the shift register (shifts data) — and a stuck sequential circuit is most often a missing or blocked clock, so check the clock first.

Skills Learned

  • You can now distinguish combinational from sequential logic and explain how a flip-flop remembers a bit.
  • You can now describe an SR latch and the difference between a latch and an edge-triggered flip-flop.
  • You can now state what a D, JK, and T flip-flop each do, including the T's divide-by-2.
  • You can now identify a register, counter, and shift register and reason about a sequential-logic fault.
  • You can now check the clock first when a clocked digital circuit is stuck.

Glossary Additions

  • sequential logic — digital logic whose output depends on both the current inputs and a stored internal state (its memory of the past), so the same inputs can give different outputs depending on what came before; it is what lets digital systems count, remember, and step through sequences. It contrasts with combinational logic, which has no memory.
  • flip-flop — a bistable digital circuit that stably stores one bit (a 1 or a 0) until told to change; it is edge-triggered, capturing its input at a clock edge, and is the basic memory element of sequential logic. Common types are SR, D, JK, and T.
  • latch — a bistable storage element built from cross-coupled gates that is level-sensitive: it follows its data input while its enable (or clock) is at the active level and holds the value when the enable goes inactive, unlike the edge-triggered flip-flop.
  • register — a group of flip-flops sharing a clock that together store a multi-bit word, all captured on the same clock edge; registers hold the values a processor or system works with, and chained or specialized forms become counters and shift registers.

Suggested Next Sections

Must read next:

  • Clock Systems and Timing — the shared heartbeat that drives all this sequential logic: how clocks are generated and distributed, and the timing rules (setup, hold, propagation) that keep a synchronous system correct.

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