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CSP — Chip Scale Package Characteristics

The area array the volume has mastered now shrinks until the package nearly disappears into the die, and this section teaches what survives the shrink and what changes. A chip scale package is defined by a ratio, not a size: the package body no larger than about 1.2 times the die inside it — packaging reduced to a rounding error on the silicon. At the limit sits the wafer-level package, where the ratio reaches 1.0 and the distinction collapses: the die is the package, its bumps applied while the silicon was still part of the wafer, a redistribution layer of thin-film wiring rerouting the die's native pads to the bump grid, and no substrate, no overmold, no armor of any kind — the component on the board is a bare piece of silicon with solder on its face. Every law the BGA chapters taught survives: the hidden field, the collective settle, the witness discipline, the bounded verification. But the shrink taxes every margin. The bare die chips at edges and cracks at faces that an overmolded BGA would shrug off. The tiny thermal mass heats fast and overshoots faster, thinning the profile margins the card design depends on. The settle's recovery envelope, which scales with ball size, shrinks in absolute terms until fine-pitch placement error and unrecoverable error nearly touch. And on the phone boards where CSPs live, underfill is not an occasional complication but the standing condition — the epoxy that makes a bare die survive a pocket also makes every removal a different operation. This section is the chapter's foundation: the packages that look like small BGAs, and the specific ways that 'small' rewrites the bench's assumptions.

AdvancedLow Risk23 min read

What You Will Learn

  • You will learn the chip-scale ratio — the definition that makes CSP a relationship between package and die, not a size class.
  • You will learn the wafer-level package — the die as its own package, with the redistribution layer that makes the bump grid possible.
  • You will learn what the shrink does to fragility — bare silicon edges and faces, with no overmold to absorb the bench's mistakes.
  • You will learn what the shrink does to heat and settle — small mass overshooting fast, and a recovery envelope that scales down with the balls.
  • You will learn the underfill condition — why phone-board CSPs arrive glued, and what that promises about every future removal.

What You Will Be Able To Do

  • You will be able to identify CSPs and WLCSPs on a real board and state the ratio evidence for the call.
  • You will be able to read a wafer-level package's anatomy — die face, edge, bump field — under magnification.
  • You will be able to reason the scaled settle — same law, smaller absolute envelope — for a given pitch.
  • You will be able to survey a board for underfill and write the removal implications before any plan is made.
  • You will be able to state which BGA disciplines carry to CSP unchanged and which arrive with thinner margins.

Required Tools

  • The microscope and loupe — this section's work is observation, and CSP evidence lives below what the eye resolves
  • A donor smartphone or wearable board — the natural habitat: CSPs in numbers, most of them underfilled
  • Grazing light — die edges, bump fields, and underfill fillets all read best at a low angle
  • The notebook — the section builds a package survey, and surveys are written, not remembered

When NOT to Attempt This

Do not attempt this section if any of the following apply to you:

  • You are not comfortable working with small surface-mount components.
  • You have not completed the prerequisite sections for this skill.
  • You do not have the required tools in working condition.

Section Overview

The array the volume mastered shrinks toward the die, and the laws survive with thinner margins (what-is-bga). The chip-scale ratio defines the class. Package no larger than about 1.2 times its die — a relationship, not a size; at 1.0, the die is the package (bga-in-modern-consumer-electronics). The wafer-level package is the limit case. Bumps applied at the wafer, no substrate, no overmold — bare silicon with solder on its face. The redistribution layer makes the grid possible. Thin-film wiring rerouting die pads to the bump array — the packaging reduced to a layer (bga-failure-modes). The shrink taxes every margin. Bare edges chip, small mass overshoots, the settle's envelope scales down with the balls (bga-repairability-assessment). And underfill is the standing condition. Phone-board CSPs arrive glued — every removal a different operation before it begins. Ratio, inversion, layer, tax, glue — the chip scale package entire.

Why This Matters

The CSP is where the volume's disciplines meet the boards most benches actually see — phones, wearables, everything pocket-sized (bga-in-modern-consumer-electronics). This matters because the ratio reframes recognition: a bench hunting for 'small BGAs' misses the point — the CSP question is how much package surrounds the die, and the answer decides fragility, thermal behavior, and what removal will cost (what-is-bga). This matters because the bare die forgives nothing: the overmold the BGA chapters never had to think about was doing quiet work — absorbing tweezers, tolerating pens, shrugging off the bench's small sins — and on a WLCSP every one of those sins lands on silicon (bga-failure-modes). It matters because thermal margins shrink with mass: a profile card that soaks a BGA gently will overshoot a CSP that weighs almost nothing, and the card design the profile section taught starts needing its margins more (bga-repairability-assessment). It matters because the settle's forgiveness is measured in ball-widths: the law is unchanged and the millimeters are smaller — fine pitch turns good placement habits from craft into survival. And it matters because underfill decides before the bench does: the glued package's removal is a different chapter of work, and the survey that finds the glue early is the survey that prices the job honestly. Same laws, smaller margins — the shrink entire.

Required Prerequisites

Before starting this section, you should have completed:

  • What Is BGA? — the area-array foundation the CSP shrinks: the hidden field, the collective settle, and the vocabulary this section scales down.
  • BGA in Modern Consumer Electronics — the device landscape where CSPs dominate: the phone and wearable boards this section reads.
  • Isopropyl alcohol and lint-free wipes — donor boards arrive dirty, and CSP evidence is small enough to hide under a fingerprint.
  • ESD-safe brushes — dust removal at magnification without adding scratches to bare die faces that this section teaches you to protect.
  • A fine probe or wooden pick — for the underfill survey: fillet edges are found by gentle touch at the package perimeter, never by force.
  • A donor smartphone board — the richest CSP habitat: power management, audio, charging silicon, most of it wafer-level and most of it underfilled.
  • A donor wearable or earbud-case board — the smaller cousins, where chip-scale packaging is not a choice but the only thing that fits.
  • A donor mid-2010s phone board for contrast — earlier boards carry larger-pitch CSPs and patchier underfill, and the contrast teaches the trend.

Real-World Applications

The CSP survey is the first hour of every modern board-level job, whether the bench names it or not. A technician triaging a phone's power-management neighborhood reads the board as this section teaches: which packages are wafer-level bare silicon, which carry underfill fillets, which sit at pitches where the settle's forgiveness is a hair's width — and the triage prices the repair before an iron warms (bga-repairability-assessment). A bench quoting a tablet's dead audio codec finds the WLCSP glued under epoxy and quotes the removal as what it is — an underfill job, not a BGA job — because the survey caught the fillet that changes the operation (bga-in-modern-consumer-electronics). A repairer examining a cracked wearable board reads die-edge chips on two bare packages under grazing light — damage an overmolded BGA would have hidden or survived — and writes the honest verdict that the silicon itself is the casualty (bga-failure-modes). And a student moving from BGA practice to phone boards discovers the disciplines transfer whole: the hidden field is still hidden, the witness still outranks memory, the verification still climbs bounded — just all of it smaller, faster, and less forgiving (what-is-bga). The confusions this prevents: a WLCSP handled like an overmolded package, a BGA profile flown over a massless die, a fine-pitch placement trusted to BGA-scale forgiveness, and an underfilled removal quoted as a clean lift.

Common Challenges

  • CSPs hide in plain sight. At a glance a WLCSP is a dark rectangle among dark rectangles — the tells are the mirror-bright silicon face, the absence of mold texture, and the laser markings that sit directly on die — and some WLCSPs wear a thin black backside film that hides the mirror, so on a matte-faced candidate fall back to the edge read and the missing substrate sandwich, which no film conceals (what-is-bga).
  • The ratio cannot be seen directly. The die hides inside anything that is not wafer-level — the call comes from package thinness, edge construction, and the habitat: what a phone board mounts at 0.4 mm pitch is chip-scale by economics alone (bga-in-modern-consumer-electronics).
  • Underfill reads as shadow. A thin epoxy fillet at a package perimeter looks like solder-mask discoloration until probed — the survey uses grazing light and a gentle pick, and trusts touch over first glance.
  • Fragility inverts handling instincts. Benches trained on overmolded packages grip, brace, and pry by habit — bare silicon punishes each of those, and the discipline is to handle the die like the unprotected part it is (bga-failure-modes).

Safety Notes

Risk Level: Low. This section heats nothing and removes nothing — its discipline is observation, and the law still stands around it.

  • ESD discipline throughout — bare-die packages expose the silicon directly; the strap and the mat are not ceremony on these boards.
  • No prying, no pressure — the underfill survey identifies the bond; breaking it belongs to a later section's tooling and plan.
  • Handle donor boards as if live — the habit that keeps real boards safe is built on the boards that do not matter.

Professional Tips Before Starting

  • Survey before magnifying. Walk the whole board at low power first, marking candidates — the package census comes before the package study, and the census is what the repair quote will lean on (bga-repairability-assessment).
  • Use the phone board's geography. Power management clusters near the battery connector, audio near the codec's passives, charging silicon near the port — the neighborhood names the package faster than the marking does (bga-in-modern-consumer-electronics).
  • Read edges, not just faces. A WLCSP announces itself at its edge: silicon's clean saw-cut edge against the laminate, no substrate sandwich, no mold lip — the edge is the ratio made visible.
  • Log pitch estimates with every entry. Pitch decides the settle's absolute forgiveness and the placement tooling later sections will demand — a survey without pitch is a list of names.

The Shrink — Ratio, Inversion, Layer, Tax, Glue

Recap and Frame

The volume arrives here fluent in area arrays: the hidden field, the settle, the witness, the bounded claim — all of it taught at BGA scale (what-is-bga). The consumer chapter set the map. Phones and wearables run on packages the BGA sections sized up — and promised the shrink would get its own chapter (bga-in-modern-consumer-electronics). The failure and repairability lenses arrive trained. What breaks and what is worth fixing were both taught on packages with substrates and armor — this chapter re-asks both questions for packages without either (bga-failure-modes). And the frame is honest. Nothing in this section is a new law — it is the old laws taxed: same physics, same disciplines, margins cut to fit a package that is mostly die (bga-repairability-assessment).

The Ratio and the Inversion — What a CSP Is

The definition is a relationship: a chip scale package is a package no larger than about 1.2 times its die — packaging as a margin around silicon, not a housing for it (what-is-bga). The ratio is a spectrum. Near-CSP packages keep a thin substrate and a skim of mold; as the ratio falls toward 1.0 the layers thin and vanish, and the classes blur into each other by construction, not by name. At 1.0 the inversion: the wafer-level package. The die is the package — bumps applied while the silicon was still part of the wafer, the part singulated afterward, and what ships is bare silicon with solder on its face (bga-in-modern-consumer-electronics). The redistribution layer is the enabler. Die pads are born where the circuit designer needed them, not where a bump grid wants them — the RDL is thin-film wiring, laid on the die face, that reroutes native pads out into the area array the board will meet. No substrate, no overmold, no interposer. Everything a BGA's package did — spreading stress, hiding the die, absorbing handling — is now done by nothing, and the bench inherits the difference (bga-failure-modes). Relationship, spectrum, inversion, rerouting, absence — the definition entire. A CSP is not a small BGA; it is a die that learned to be its own package, and the difference is the chapter.

The Tax — Fragility, Heat, and the Scaled Settle

The laws survive the shrink; the margins pay for it (bga-repairability-assessment). Fragility is the visible tax. Bare silicon chips at edges and cracks at faces — the tweezers grip, the pen's off-center press, the brace against a neighbor that an overmolded BGA absorbs without record, each lands directly on the component's own body (bga-failure-modes). Heat is the fast tax. A package that weighs almost nothing has almost no thermal inertia: it follows the air's temperature instead of lagging it, overshoots where a BGA would soak, and thins every margin the profile card design counted on — the card still rules, but its stages must respect a mass that answers instantly (what-is-bga). The settle is the quiet tax. The law is untouched — molten balls, collective surface tension, translation recovered within a fraction of the pad — but the fraction is of a smaller pad: at fine pitch the same forgiving physics forgives a smaller absolute distance, and the gap between recoverable offset and wrong-pad disaster narrows to a hair (bga-in-modern-consumer-electronics). Inspection pays too. Standoff shrinks with the balls, the edge peek's viewing angle collapses, and the perimeter read that verified a BGA becomes a sliver of light under a CSP — the instruments carry over with narrower reach. Edges, inertia, envelope, sightline — the tax entire. Every discipline the volume taught still works; the shrink just spends the slack the bench used to live on.

The Glue — Underfill as the Standing Condition

On the boards where CSPs live, underfill is not a complication — it is the default the survey must assume until disproven (bga-in-modern-consumer-electronics). The glue exists because the bare die must survive a pocket. Drop stress that a substrate would spread now concentrates in the outermost bumps; the epoxy under the die turns a bump field into a bonded joint, and the phone that survives its first fall owes the survival to the fillet (bga-failure-modes). The fillet is the survey's target. A thin, glossy or matte bead at the package perimeter, wicked under by capillary action at manufacture and cured hard — found under grazing light, confirmed by a gentle probe at the edge, and logged package by package. The glue rewrites removal before removal is planned. A free package lifts when its field melts; a glued package is held by cured thermoset that no reflow softens usefully — even the minority of underfills sold as reworkable release only with sustained heat plus deliberate mechanical work and residue cleanup, never as a clean lift — its removal is a heat-and-mechanics operation of its own class — never priced as a clean lift, which is exactly how quotes go wrong (bga-repairability-assessment). The survey writes it down. Which packages are glued, where the fillets run, what the removal class of each would be — the page the repairability call opens first (what-is-bga). Default, reason, fillet, rewrite, record — the glue entire. Underfill is the board announcing its repair difficulty in advance — the bench that reads the announcement quotes the truth.

Common Mistakes

  • Treating a CSP as a small BGA. The name is a ratio, not a nickname — the bare die, the massless thermal response, and the scaled settle each break a BGA habit, and the bench that keeps all its habits breaks packages (what-is-bga).
  • Gripping bare silicon like molded plastic. Tweezers at the edges, pens pressed off-center, braces against the face — the overmold that forgave those is not there; the die is the surface (bga-failure-modes).
  • Flying BGA profiles over CSP mass. The card that soaks a gram of package overshoots a package that weighs a fraction of it — profiles answer to thermal mass, and this mass is nearly zero (bga-repairability-assessment).
  • Trusting BGA-scale settle forgiveness at fine pitch. The physics is identical and the millimeters are not — at 0.4 mm pitch, the recoverable offset and the wrong-pad offset are neighbors.
  • Missing the underfill until the removal fails. The fillet found mid-lift is a package destroyed and a quote broken — the survey runs first, and the glue is a plan input, not a surprise (bga-in-modern-consumer-electronics).

Troubleshooting Guidance

  • Cannot tell WLCSP from small molded package — the face and the edge decide: silicon's mirror face and clean diced edge against mold compound's matte texture and lip; if the marking sits laser-etched directly on a reflective face, the die is the package (what-is-bga).
  • Underfill suspected but not confirmed — light, then touch: grazing light for the fillet's bead, a gentle wooden pick at the perimeter for the hard-cured ridge; a package that shows neither on all reachable sides is provisionally free, and the log says 'provisionally' (bga-repairability-assessment).
  • Die-edge chip found during survey — record before judging: small chips at the outer edge may be cosmetic or may have reached active silicon; the honest entry photographs it, notes position and size, and lets the failure lens decide whether the package is evidence or casualty (bga-failure-modes).
  • Pitch too fine to estimate under available magnification — use the neighbors: count bumps against a known package dimension or the board's own reference features; a pitch logged as 'approximately 0.4 by bump count' beats a blank field (bga-in-modern-consumer-electronics).

Verification & Testing Methods

Confirm your CSP fluency before calling this section complete:

  • [ ] I can identify a package as chip-scale by the chip-scale ratio evidence — thinness, edge construction, habitat — and state the call's basis.
  • [ ] I can read a wafer-level package under magnification — bare face, diced edge, bump field — and distinguish it from molded construction.
  • [ ] I can explain the redistribution route — die pads to bump grid through the redistribution layer — and why the die needed it.
  • [ ] I can survey a board for underfill with light and gentle touch, and log each package's removal class honestly.
  • [ ] I can state which BGA disciplines carry unchanged and which margins the shrink taxes — fragility, heat, settle, sightline.

Then try the practice exercises below — observation and desk work only; scenarios differ from the quiz.

Practice Exercises

  1. Run the package census (5 minutes, donor phone board at low power). Walk the whole board and mark every area-array candidate, then sort them: molded BGA, chip-scale with visible package layers, wafer-level bare die — with the ratio evidence for each call written beside it (what-is-bga).
  2. Read one WLCSP's anatomy (5 minutes, highest available magnification). Pick one wafer-level package from the census and log its construction: the mirror face and its laser marking, the diced edge against the laminate, the bump field's extent and estimated pitch — the anatomy read that distinguishes die-as-package from packaged die (bga-in-modern-consumer-electronics).
  3. Reason the scaled settle (5 minutes, desk work from the census). For the largest and smallest pitches logged, work the comparison: the same fraction-of-pad recovery as an absolute distance at each pitch, and a written sentence on what the difference demands of placement — the law unchanged, the margin priced (bga-repairability-assessment).
  4. Map the underfill (5 minutes, grazing light and a gentle pick). Survey every census package for fillets — light first, touch second, no force — close the survey document — each package's removal class written as free, glued, or provisional, with the honest note on what the glued ones will someday cost — and write the survey's closing verdict: which BGA disciplines this board's CSPs inherit unchanged, and which margins the shrink has taxed — fragility, heat, settle, sightline (bga-failure-modes).

These core steps — the census, the anatomy read, the scaled-settle reasoning, the underfill map, and the carry-and-tax verdict — are tested in the Chapter Quiz at the end of this chapter, where a score of 80% is required to continue.

Key Takeaways

  • The chip-scale ratio defines the class — package no larger than about 1.2 times its die, a relationship the bench reads from thinness, edges, and habitat rather than a size chart (what-is-bga).
  • The wafer-level package is the limit case — the die as its own package, bumped at the wafer, shipped bare, with everything the overmold used to absorb now landing on silicon (bga-failure-modes).
  • The redistribution layer makes the array possible — thin-film wiring rerouting native die pads to the bump grid, packaging reduced to a layer on the die's own face.
  • The shrink taxes every margin — fragility at the edges, overshoot in the massless thermal response, a settle envelope that scales down with the balls, and an edge peek narrowed to a sliver (bga-repairability-assessment).
  • Underfill is the standing condition on CSP boards — the glue that lets bare dies survive pockets, found by survey before any plan, and the single fact that most changes what a removal will cost (bga-in-modern-consumer-electronics).

Skills Learned

After completing this section, you can:

  • Identify chip-scale and wafer-level packages on real boards and defend the call with construction evidence.
  • Read a WLCSP's anatomy — face, edge, bump field, pitch — under magnification.
  • Price the shrink's tax on fragility, thermal response, and settle forgiveness for a given package.
  • Survey a board for underfill and classify every package's removal class before planning.
  • State precisely which BGA disciplines transfer to CSP work unchanged and which need their margins re-derived.

Glossary Additions

New terms introduced in this section:

  • chip-scale ratio — the defining relationship of the chip scale package: a body no larger than about 1.2 times the area of the die inside it, packaging reduced to a margin around the silicon rather than a housing for it. The ratio is a spectrum — near-chip-scale packages keep a thin substrate and a skim of mold, and as the ratio falls toward 1.0 the layers thin until the wafer-level limit, where the die is the package and the distinction collapses. The bench reads the ratio indirectly: package thinness, edge construction, and habitat, because what a phone board mounts at fine pitch is chip-scale by economics before any measurement.
  • wafer-level package — the chip scale package at ratio 1.0: the die is the package, its solder bumps applied while the silicon was still part of the wafer and the part singulated afterward. What ships is bare silicon with solder on its face — no substrate, no overmold, no armor — so everything a conventional package absorbed lands on the die itself: handling chips its edges, pressure cracks its face, and a static hit reaches active silicon through the bumps. Recognized under magnification by the mirror-bright face with laser marking directly on it and the clean diced edge against the board.
  • redistribution layer — the thin-film wiring laid on a die's face that reroutes its native pads — born where the circuit design needed them — out into the area-array bump grid the board requires. The RDL is what makes wafer-level packaging possible: it is the entire 'package' of a WLCSP reduced to a metallization layer, and it is why a bare die can present the same hidden-field geometry as a full BGA — the array is real, but the packaging around it has thinned to a layer measured in microns.

Suggested Next Sections

Must read next:

  • LGA — Land Grid Array Repair — Section 6.2 turns to the array with no balls at all: solder on the board side of the equation, and the repair craft that manages paste where spheres used to be.

Recommended:

  • BGA Failure Modes — the failure lens this section's fragility and underfill discussions lean on, taught at the scale where it began.
  • BGA Repairability Assessment — the decision discipline the CSP survey feeds: what the glue, the pitch, and the bare die do to the worth-fixing call.